1. Field of the Invention
The present disclosure relates to a high light transmittance in-plane switching liquid crystal display device and a method for manufacturing the same. Especially, the present disclosure relates to a horizontal electric field type liquid crystal display device having the horizontal electric fields over the pixel electrodes and the common electrodes which are disposed on the same level plane, and a method for manufacturing the same.
2. Discussion of the Related Art
Nowadays, various flat panel display devices are developed for overcoming many drawbacks of the cathode ray tube such as heavy weight and bulk volume. The flat panel display devices include the liquid crystal display device (or LCD), the field emission display (or FED), the plasma display panel (or PDP) and the electroluminescence device (or ED).
The liquid crystal display device represents video data by controlling the light transmitivity of the liquid crystal layer using the electric fields. According to the direction of the electric field, the LCD can be classified in the two major types; one is vertical electric field type and the other is the horizontal electrid field type.
For the vertical electric field type LCD, the common electrode formed on the upper substrate and the pixel electrode formed on the lower substrate are facing with each other for forming the electric field of which direction is perpendicular to the substrate face. The twisted nematic (TN) liquid crystal layer disposed between the upper substrate and the lower substrate is driven the vertical electric field. The vertical electric field type LCD has merit of higher aperture ratio, while it has demerit of narrower view angle about 90 degree.
For the horizontal electric field type LCD, the commone electrode and the pixel electrode are formed on the same substrate in parallel. The liquid crystal layer disposed between the upper substrate and the lower substrate is driven in In-Plane-Switching (IPS) mode by the electric field parallel to the substrate face. The horizontal electric field type LCD has a merit of wider view angle over 170 degrees and faster response speed than the vertical electric field type LCD.
Hereinafter, we will explain about the horizontal electric field type LCD. FIG. 1 is a plane view illustrating the horizontal electric field type liquid crystal display device according to the related art. FIGS. 2A to 2D are cross-sectional views illustrating the steps of manufacturing the horizontal electric field type liquid crystal display panel of FIG. 1 by cutting along the line I-I′ according to the related art.
Referring to FIG. 1 and FIGS. 2A to 2D, the liquid crystal display panel includes a thin film transistor array substrate having a plurality of thin film transistors thereon. The liquid crystal display panel, not shown in the drawings, further includes a color filter substrate facing with the thin film transistor substrate and a liquid crystal layer between the thin film transistor substrate and the color filter substrate. The color filter substrate includes a plurality of color filters and a black matrix.
The thin film transistor substrate of the horizontal electric field type LCD panel comprises a gate line GL and a data line DL crossing each other on a lower substrate SUB, a thin film transistor TFT formed at the crossing portion of the gate line GL and the data line DL, a pixel electrode PXL and a common electrode COM formed within a pixel area defined by the crossing structure of the gate line GL and the data line DL to form a horizontal electric field, and a common line CL connecting to the commone electrode COM.
The thin film transistor TFT includes a gate electrode G branching from the gate line GL, a semiconductor layer A overlapping with the gate electrode G on a gate insulating layer GI covering the gate electrode G, a source electrode S branching from the data line DL and contacting one side of the semiconductor layer A, and a drain electrode D facing with the source electrode and contacting the other side of the semiconductor layer A. On the thin film transistor TFT, a passivation layer PASSI is formed to cover and protect the thin film transistor TFT. On the passivation layer PASSI, the pixel electrode PXL and the common electrode COM are formed.
The gate line GL supplies the gate signal to the gate electrode G. The data line DL supplies the pixel signal to the pixel electrode PXL through the drain electrode D of the thin film transistor TFT. The gate line GL and the data line DL are formed in the crossing structure to define the pixel area. The common line CL is formed to be parallel to the gate line GL with the pixel area between the gate line GL, and supplies the reference voltage signal for driving the liquid crystal layer to the common electrode PXL.
The thin film transistor TFT charges and maintains the pixel signal voltage to the pixel electrode PXL by responding to the gate signal of the gate line GL. The pixel electrode PXL is formed within the pixel area to be connected to the drain electrode D of the thin film transistor TFT exposed via a drain contact hole CHD formed through the passivation layer PASSI. The common electrode COM is formed within the pixel area to be connected to the common line CL via a common contact hole CHCOM formed through the passivation layer PASSI and the gate insulating layer GI. Especially, the pixel electrode PXL and the common electrode COM are disposed in parallel with each other within the pixel area. For example, the common electrode COM has a plurality of vertical segments which are separatedly disposed with a predetermined distance each other. The pixel electrode PXL has a plurality of vertical segments in which each segments is disposed between the segments of the common electrode COM.
Therefore, the horizontal electric field is formed between the pixel electrode PXL supplied with the pixel signal voltage through the thin film transistor TFT and the commone electrode COM supplied with the reference signal voltage through the common line CL. Due to this horizontal electric field, the liquid crystal molecules of the liquid crystal layer disposed between the thin film transistor array substrate and the color filter substrate are rotated by the dielectric anisotropy. According to the rotating amount, the light transmittance of the pixel area is differed, and then the video image can be represented.
Referring to FIG. 1 and FIGS. 2A to 2D, the processing of manufacturing the horizontal electric field type liquid crystal display panel will be explained. This manufacturing process has four mask-processes which are mostly stabilized processing method in current technology.
A gate metal is deposited on a substrate SUB. The gate elements are formed by patterning the gate metal using the first mask process. As shown in FIG. 2A, the gae elements include the gate line GL, the gate electrode G branching from the gate line GL, a gate pad GP formed at one end of the gate line GL, and the common line CL disposed in parallel to the gate line GL.
A gate insulating layer GI is deposited on the whole surface of the substrate SUB having the gate elements. After that, a semiconductor material and a source-drain metal are sequentially deposited thereon. By patterning the semiconductor material and the source-drain metal using the second mask process, the source-drain elements are formed. As shown in FIG. 2B, the source-drain elements include the data line DL crossing with the gate line GL, a data pad DP formed at one end of the data line DL, the source electrode S branching from the data line DL and overlapping with one side of the gate electrode G, and the drain electrode D facing with the source electrode S and overlapping with the other side of the gae electrode G. Especially, the source electrode S and the drain electrode D are physically separated eath other, but they are connected via the semiconductor layer A formed on the gate insulating layer GI and overlapping with the gate electrode G under the source electrode S and the drain electrode D. The source-drain metal between the source electrode S and the drain electrode D are removed, but the semiconductor layer under the removed source-drain metal should be remained. Therefore, it is preferable to use the half-tone mask. That is, the semiconductor material is remained under the source-drain elements, and it does not work. The semiconductor material between the source electrode S and the drain electrode D just plays role as a semiconductor channel layer A. In the interim, as shown in FIG. 1, the drain electrode D can be formed as to be overlapped with the common line CL. In this case, the overlapped portion with the drain electrode D can play role as a storage capacitance Cst.
On the whole surface of the substrate SUB having the source-drain elements, the passivation layer PASSI is deposited. As shown in FIG. 2C, by patterning the passivation layer PASSI using the third mask process, the drain contact hole CHD exposing some portions of the drain electrode D and a data pad contact hole CHDP exposing some portions of the data pad DP are formed. At the same time, by patterning the passivation layer PASSI and the gate insulating layer GI, a gate pad contact hole CHGP exposing some portions of the gate pad GP is formed. Furthermore, not shown in the cross sectional views, the common contact hole CHCOM exposing some portions of the common line CL is formed.
On the passivation layer PASSI having the contact holes CHGP, CHD, CHDP and CHCOM, a transparent conductive material such as ITO (Indium Tin Oxide) is deposited. By patterning the transparent conductive material using the fourth mask process, the pixel electrode PXL and the common electrode COM are formed within the pixel area. At the same time, a gate pad terminal GPT contacting the gate pad GP through the gate pad contact hole CHGP, and a data pad terminal DPT contacting the data pad DP through the data pad contact hole CHDP are formed. The pixel electrode PXL contacts the drain electrode D through the drain contact hole CHD. The common electrode COM contact the common line CL through the common contact hole CHCOM. The pixel electrode PXL and the common electrode COM are disposed in parallel each other with a predetermined distance, as shown in FIG. 2D.
After that, even not shown in drawings, the thin film transistor array substrate having the pixel electrode PXL and the common electrode COM will be transferred to the chamber for forming the alignment layer. And then, the thin film transistor array substrate is joined with the color filter array layer by having the liquid crystal layer therebetween to complete the liquid crystal display panel.
In the horizontal electric field type liquid crystal display panel mentioned above, the formation of the horizontal electric field for driving the liquid crystal layer will be explained in detail. FIG. 3 is the cross-sectional view illustrating the formation of the horizontal electric field for driving the liquid crystal molecules formed between the pixel electrode and the common electrode in the horizontal electric field type liquid crystal display panel according to the related art, by cutting along the line II-II′ in FIG. 1.
Referring to FIG. 2, the pixel electrode PXL and the common electrode COM are disposed in parallel at the same leveled plane. When there is a DC voltage difference between the pixel electrode PXL and the common electrode COM, the horizontal electric field is formed as the solid curve as shown in FIG. 3. As above explained, the pixel electrode PXL and the common electrode COM have the rectangular segment shape. The pixel electrode PXL and the common electrode COM are disposed in facing with a predetermined distance.
In the horizontal electric field type liquid crystal display panel currently used in most, as shown in FIG. 3, the pixel electrode PXL and the common electrode COM are the segment shape having about 4 um (micro-meter) line width. The pixel electrode PXL and the common electrode COM are separated each other with about 10˜12 um distance which is about 2.5˜3 times of the line width. In addition, on the pixel electrode PXL and the common electrode COM, the alignment layer ALG defining the initial alignment direction of the liquid crystal molecules LCM of the liquid crystal layer is deposited.
When the electric field is formed between the pixel electrode PXL and the common electrode COM, the liquid crystal molecules LCM are rearranged along the direction of the electric field. Under this condition, the horizontal electric field is formed within the space between the closest sides of the pixel electrode PXL and the common electrode COM. However, right over the pixel electrode PXL and the common electrode COM, there is no horizontal electric field but almost vertical electric field.
Under this condition, as shown in FIG. 3, most of liquid crystal molecules LCM disposed right over the pixel electrode PXL and the common electrode COM are not rearranged by the electric field but maintained in the initial alignment direction. That is, the liquid crystal molecules LCM disposed between the pixel electrode PXL and the common electrode COM are driven by the horizontal electric field to contribute to the variation of the light transmittance. However, the liquid crystal molecules LCM right over the pixel electrode PXL and the common electrode COM are not driven by the horizontal electric field so they do not contribute to the variation of the light transmittance. Therefore, the areas occupied by the pixel electrode PXL and the common electrode COM are the non-display area NDA, and the areas of the space between the pixel electrode PXL and the common electrode COM are the display area DA only.
In the vertical electric field type, the whole overlapped areas of the pixel electrode PXL and the common electrode COM in the pixel area contribute to the aperture ratio and the brightness directly. However, in the horizontal electric field type, the areas of the pixel electrode PXL and the common electrode COM do not contribute to the aperture ratio and the brightness directly. Even though the pixel electrode PXL and the common electrode COM are made of transparent material, they reduce the aperture ratio and the brightness.